1. Field of the Invention
The present invention relates to clock distribution circuits.
2. Description of the Related Art
Along with increasing miniaturization of semiconductor integrated circuits in recent years, problems of manufacturing discrepancies brought about by new factors that did not require consideration at the design stage are exerting a large influence on circuit designs in conventional semiconductor processes.
In the processes of generations where miniaturization was not so far advanced, the statistical distribution of individual differences caused by lots, wafers, materials, and the like were generally handled as discrepancies. In the processes of advanced miniaturization of the 90 nm generations onward, in addition to the aforementioned individual differences, it has also become necessary to give consideration at the design stage to individual differences of transistors and wiring within a chip due to voltage drops and machining accuracy as factors of timing discrepancies.
That is, since these factors of discrepancies influence the design values of timing, design constraints must be added of including greater timing margins. In particular, differences in electrical properties are a direct adverse factor of clock skew, and in locations such as interfaces between blocks having long distances from the clock branch, timing margins as countermeasures of discrepancies applied to route differences use an undesirably large portion of the timing in the cycle time.
In regard to these circumstances, methods are being investigated in which when clock-based synchronization circuits are designed, the phases of sequential circuits of terminals driven by a clock are adjusted using multiple phase adjustment mechanisms such as PLLs or DLLs within a chip. Forms of implementation such as those disclosed in Japanese Patent Laid-Open No. 2008-010607 for example can be used as such a method.
Here, generally a delay of a feedback loop is used in the mechanism of phase adjustments for PLLs and DLLs and the like. However, there is a probability that phase adjustments will be insufficient if routes to sequential circuits of terminals driven by the clock are designed independently.
For this reason, forms of implementation such as those described in Japanese Patent Laid-Open No. 2007-336003 for example are conceivable as methods of using a portion of a clock route to a specific sequential circuit as a shared route of a feedback loop.
However, there are currently further advances being made in miniaturization and it is necessary to give consideration at the design stage up to problems of discrepancies occurring in manufacturing processes such as exposure of mask patterns and the forming and polishing of thin films that constitute elements and wiring.
That is, even if circuits are laid out using exactly the same structure of elements and wiring, discrepancies in the manufacturing processes cannot be ignored in which shapes and electrical properties change undesirably at the manufacturing stage due to the positions of placement and the patterns of peripheral circuits.
Since systematic factors and random factors are both related in the influence of discrepancies occurring in manufacturing processes, it is difficult to accurately estimate these at the design stage.
Here, in conventional feedback loop path forming methods of phase adjustment mechanisms such as PLLs and DLLs, there is increased sharing of many of the clock routes and phase information of sequential circuits of the terminals is fed back. However, in processes where greater miniaturization is implemented, the influence of discrepancies that occur between the clock drivers and the wiring within independent routes after the feedback path branch cannot be ignored. Accordingly, it is difficult with conventional techniques to eliminate completely problems of discrepancies, and reduced precision in phase adjustments is anticipated.
Japanese Patent Laid-Open No. 2007-336003 discloses, as shown in FIG. 1, clock distribution circuits 11a and 11b that are provided with a clock generation circuit 13 having multiple DLLs or PLLs or the like, and are configured with clock distribution networks 12a and 12b (and 14; abbreviated as “CDN”) for each of the clock generation circuits 13 respectively. Routes 17a and 17b are provided that perform feedback from branch points NA1 and NB1 of the sequential circuits (abbreviated as “SC”) 16a and 16b having a data transfer path 18 connecting between the sequential circuits belonging to the clock distribution networks 12a and 12b (clock domains) whose clock generation circuits 13 are different.
Here, description is given giving attention to a single block 10a. 
Positions where the branch points that carry out feedback are provided are determined in a following manner. These are determined such that a delay of the path from the feedback branch point NA1 to the clock input terminal of the sequential circuit 16a and a delay from the feedback branch point NA1 to the feedback clock terminal of the clock generation circuit 13 become zero. In terms of positions, branch points are selected so as to be as close as possible to a leaf so that the delay time difference becomes small.
Japanese Patent Laid-Open No. 2007-336003 gives consideration to discrepancies of delay times in manufacturing processes. The delay from a CLKOUT of the clock generation circuit 13 to a clock input of the sequential circuit 16a varies from an ideal design value. Similarly, the delay from the CLKOUT of the clock generation circuit 13 to an FBK terminal of the clock generation circuit 13 also varies from an ideal design value. Here, by using a configuration such that from the CLKOUT of the clock generation circuit 13 to the branch point NA1 is shared, the discrepancies of the shared portion can be accurately reflected in the phase adjustments of the clock generation circuits 13.
However, a difference occurs between the delay from the branch point NA1 to the clock input of the sequential circuit 16a and the delay from the branch point NA1 to the FBK terminal of the clock generation circuit 13.
In methods of forming conventional feedback circuits, the branch point NA1 is provided at the clock driver input terminal side closest to the sequential circuit. Thus, a clock driver (abbreviated as “CD”) 15a2 is required within the feedback path 17 so as to match the delay time from the branch point NA1 to the sequential circuit 16a and the delay time from the branch point NA1 to the clock generation circuit 13. As a result, the clock driver 15a2 within the feedback path is influenced by discrepancies. A difference occurs between a delay time A1 from the branch point NA1 to the clock input of the sequential circuit 16a and a delay time A2 from the branch point NA1 to the FBK terminal of the clock generation circuit 13, such that correct phase information cannot be fed back and the accuracy of phase adjustments is reduced undesirably (see FIG. 2). When discrepancies occur within the feedback path, all the sequential circuits within the clock distribution network are influenced undesirably and there is a probability that the accuracy of phase adjustments will be reduced undesirably.
Furthermore, consideration is not given to the physical distance between the clock generation circuit 13 and the branch point NA1. Thus there is a probability that the feedback path 17 will become long and the wiring itself (wires wf1 and wf2) of the feedback path 17 will be influenced by discrepancies, and a difference occurs undesirably in the delay times, which will be a factor of reduced accuracy in phase adjustments.